The present invention relates to a non-volatile semiconductor memory device having a MOS structure using a memory cell having a charge storage layer such as a floating gate or the like, and a control gate, and particularly, to a semiconductor memory device in which the distance between adjacent data line contacts each other is widened so that error operations can be avoided.
Conventionally, in the field of non-volatile semiconductor memory devices, an electrically re-writable non-volatile semiconductor memory device is known as an EEPROM.
This kind of EEPROM has a memory cell array in which memory cell transistors are arranged at cross points where line wires and row wires cross each other. A memory cell transistor normally has a MOS structure in which a floating gate and a control gate are layered on each other.
Among EEPROMs, a NAND type EEPROM is known as a method suitable for high integration.
FIG. 1 is a plan view showing an example of a conventional NAND type EEPROM. FIG. 2 is a cross-section cut along a line II--II in FIG. 1. FIG. 3 is a cross-section cut along a line III--III in FIG. 1. FIG. 4 is a cross-section cut along a line IV--IV in FIG. 1. In addition, FIG. 5 shows an equivalent circuit of FIG. 1.
In an NAND type EEPROM, a plurality of memory cell transistors 11 are connected in series to form a unit NAND cell. As shown in FIGS. 1 to 5, the drain side of a NAND cell is connected to data lines DL1, DL2, and DL3 through a transistor 12, while the source side of the NAND cell is connected to a source line SL through a transistor 12.
Normally, data line DL1, DL2, and DL3 are made of a semiconductor including metal or impurities at a high density, on an inter-layer insulating film 51 covering a memory cell transistor 11, and are connected to the transistor 12 in the drain side of the NAND cell.
By thus providing a plurality of NAND cells, a memory cell array is constructed. In the figures, reference 1 denotes a semiconductor substrate, and reference 2 denotes an element separation region. Reference 3 denotes a gate insulating film, and reference 4 denotes a source-drain diffusion layer. Reference 5 denotes a floating gate. Reference 6 denotes a selection gate. Reference 7 denotes a control gate. References SGD1 and SGD2 denote gate lines in the drain side. SGS1 and SGS2 denote gate lines in the source side. References CG1 to CG8 denote control gate lines.
Next, steps of forming data line contacts CD1, CD2, and CD3 and data lines DL1, DL2, and DL3 will be briefly explained below.
A memory cell transistor 11 is formed on a semiconductor substrate 1, and thereafter, the entire substrate is covered with an inter-layer insulating film 51. Thereafter, data line contacts are patterned by a photolithography method and the inter-layer insulating film 51 is etched to open contacts.
Thereafter, a material to form data lines, e.g., aluminum is deposited and patterning is carried out by a photolithography method. Data line contacts CD1, CD2, and CD3 and data lines DL1, DL2, and DL3 are formed in the steps described above.
However, in accordance with high integration of elements, the distance between adjacent NAND cells is narrowed, and then, data line contacts CD1, CD2, and CD3 as well as data lines DL1, DL2, and DL3 are arranged to be close to each other, so that processing has become more difficult and causes an error in operation. For example, short-circuiting of wires tends to easily occur due to errors in formation of a resist pattern in steps of forming data lines DL1, DL2, and DL3 by a photolithography method or in etching of a conductive material used for wires.
In addition, the widths of data lines DL1, DL2, and DL3 to be connected with data line contacts CD1, CD2, and CD3 are normally designed to be larger than the opening diameter of each contact hole. This is performed so as to allow dimension errors in alignments, which are caused in a photolithography step and an etching step. In this case, the interval distance between adjacent data lines DL1, DL2, and DL3 is much narrower than the interval distance between the data line contacts CD1, CD2, and CD3. It is therefore more difficult to perform processing so that each of the data lines and contacts might not be short-circuited.
On the same grounds as described above, the width of a portion such as a transistor 12 or the like to be connected to the data line contacts CD1 to CD3 is designed to be larger than the opening diameter of each contact hole, in several cases. In this case, the interval distance between adjacent element regions is narrowed, so that formation of an element separation region 2 is affected. For example, a punch-through occurs between adjacent element regions, rendering it difficult to obtain a electric separation. In order to avoid this situation, the width of the element separation region 2 must be widened, thereby obstructing high integration of elements.
Thus, in accordance with high integration of elements, short-circuiting of wires tends to easily occur at data line contacts CD1 to CD3 or at data lines DL1 to DL3, or punch-through tends to easily occur between adjacent element regions, resulting in a problem that processing steps are rendered difficult.
In this respect, in the prior art, a proposal has been made with respect an EEPROM in which the interval distance between adjacent data line contacts CD1 to CD3 can be widened by arranging the lay-out.
For example, FIGS. 6 to 10 show another example of a conventional NAND type EEPROM. FIG. 6 is a plan view thereof. FIG. 7 is a cross-section cut along a line VII--VII in FIG. 6. FIG. 8 is a cross-section cut along a line VIII--VIII in FIG. 6. FIG. 9 is a cross-section cut along a line IX--IX in FIG. 6. FIG. 10 shows an equivalent circuit of FIG. 6.
A data line contact CD1 is provided at a first memory cell row constructed by connecting a plurality of memory cell transistors 11 formed on a semiconductor 1. A data line contact CD2 is provided at a second memory cell row constructed by connecting a plurality of memory cell transistors 11, formed on the semiconductor substrate 1, so as to be adjacent to the first memory cell row with an element separation region 2 inserted therebetween. The data line contacts CD1 and CD2 are arranged to be shifted from each other.
In the figures, the portions corresponding to portions shown in FIGS. 1 to 5 are denoted by same references and explanation thereof will be omitted herefrom.
However, in this method, the distance between gate lines SGD1 and SGD2 forming a transistor 12 is widened, so that the periodicity of the array of control gate lines CG1 to CG4 and gate line SGD1 to SGD2 which form memory cell transistors 11 is disturbed in the vicinity of the data line contacts CD1 to CD3, resulting in a possibility of affecting manufacturing steps. For example, the flatness of an inter-layer insulating film 51 is degraded in the vicinity of the data line contacts CD1 to CD3. Since the film thickness of an inter-layer insulating film 51 is reduced so that the surface of the inter-layer insulating film 51 is recessed, it is difficult to perform patterning with use of a photolithography method, resulting in a possibility of causing short-circuiting of wires between the data lines DL1 to DL3 or between data lines DL1 to DL3 and gate lines SGD1 to SGD2.
In addition, since the interval distance between the gate lines SGD1 and SGD2 forming transistors 12 is widened, it is difficult to selectively etch only the inter-layer insulating film 51 so that data line contacts CD1 to CD3 are formed in a self-alignment manner.
Thus, in conventional data line contacts provided at a plurality of memory cell rows disposed to be adjacent to each other with an element separation region inserted therebetween, the interval distance between adjacent rows is so small that short-circuiting of wires easily occurs in accordance with high integration of elements, and a problem that the flatness of an inter-layer insulating film is degraded occurs if the interval distance is widened.